The present invention relates to multi-phase converters and more particularly to current sharing among phases in the multi-phase converters.
FIG. 1 illustrates a representative circuit topology for a multi-phase converter designated generally at 2. This includes a plurality of interleaving output phases 5a, 5b, 5c, . . . , 5n, a multi-phase converter control circuit 3, and a feedback circuit (not shown) of any suitable design, as will be understood by those skilled in the art. Each output phase includes a high-side switch, a low-side switch, and an output inductor, La, Lb, Lc, . . . , Ln. An output capacitor C is connected to the output inductors L and a load 7.
Normally, to pursue the best ripple current cancellation in both input and output sides of the multi-phase converter, such as in FIG. 2, each phase, i.e., phases 5a, 5b, 5c, . . . , 5n, is turned ON sequentially with a fixed phase shift. In several implementations, these phases 5 form a close loop and are turned ON sequentially by a shared clock signal.
Likewise, a current share bus of the multi-phase converter is normally implemented to achieve current balance or current sharing among the phases and a current share loop bandwidth is far below the outmost voltage loop bandwidth. Due to the slow current share loop in such multi-phase converters, one phase may receive a very high current and its inductor will be saturated during load transient. Use of current sharing and current share loops is well known and will be understood by those skilled in the art. A discussion of the current share loop may be found, for example, in U.S. Pat. No. 6,912,144 to Clavette.